The present invention relates to a stack package, and more particularly to a molded reconfigured wafer which simplifies the manufacturing process and decreases manufacturing costs, a stack package using the same, and a method for manufacturing the stack package.
Packaging technology for a semiconductor integrated device has continuously been developed to allow for miniaturization and high capacity. Recently, various techniques for stack packages capable of satisfying the demand toward miniaturization, high capacity and mounting efficiency have been developed.
The term “stack” as used in the semiconductor industry means to vertically place at least two semiconductor chips or packages. Stack technology, in the case of a memory device, it is possible to realize a product having a larger memory capacity that which is obtainable through a semiconductor integration process as well as an increased efficiency in usage of the mounting area.
Depending upon the manufacturing technology, stack packages are divided into a first type, in which individual semiconductor chips are stacked and the stacked semiconductor chips are packaged together at once, and a second type in which individual, separately packaged semiconductor chips are stacked. The stack packages use metal wires or through-silicon vias to electrically connect semiconductor chips to one another.
FIG. 1 is a cross-sectional view illustrating a conventional stack package using metal wires.
Referring to FIG. 1, in a stack package 100 using metal wires, at least two semiconductor chips 110 are stacked on a substrate 120 by adhesives 114. The respective chips 110 and the substrate 120 are electrically connected to each other by metal wires 116.
In FIG. 1, the unexplained reference numeral 112 designates bonding pads, 122 connection pads, 124 ball lands, 126 circuit wirings, 170 outside connection terminals, and 190 an encapsulant.
However, in the conventional stack package using the metal wires, since electrical signals are transmitted through the metal wires, signal exchange speed is slow, and since a number of metal wires are used, the electrical characteristics of the respective chips are likely to deteriorate. Further, because an additional area is required in the substrate to form the metal wires, the size of the package increases, and because a gap is required to bond the metal wires to the bonding pads, the overall height of the package increases.
Therefore, in order to overcome the problems caused in the stack package using the metal wires, prevent the electrical characteristics of the stack package from deteriorating and enable miniaturization of the stack package, a stack package using through-silicon vias has been suggested in the art.
FIG. 2 is a cross-sectional view illustrating a conventional stack package using through-silicon vias.
Referring to FIG. 2, in a stack package 200 using through-silicon vias, semiconductor chips 210, which are formed therein with through-silicon vias 230, are stacked on a substrate 220 such that the corresponding through-silicon vias 230 are connected to each other.
In FIG. 2, the unexplained reference numeral 212 designates bonding pads, 222 connection pads, 224 ball lands, 226 circuit wirings, and 270 outside connection terminals.
In the stack package using through-silicon vias, since electrical connections are formed through the through-silicon vias, degradation of the electrical characteristics of the semiconductor chips is prevented, the operating speed of the semiconductor chips is increased, and miniaturization is enabled.
However, in the conventional stack package using through-silicon vias, the through-silicon vias must be formed to pass through the semiconductor chips, and a circuit cannot be formed in the portions of the semiconductor chips where the through-silicon vias are formed. Therefore, the complicated nature of the manufacturing process increases the processing costs, and since it is necessary to fabricate wafers by designing semiconductor chips contemplating the through-silicon vias, wafers including widely used semiconductor chips cannot be used.